Technical Program

Program Sessions: Friday May 31st 2:00 PM – 5:05 PM

Session 31: Advances in Flip Chip and Chip Scale Packages
Committee: Packaging Technologies
Room: Room: Aurora B

Session Co-Chairs:

Luu Nguyen
Psi Quantum
Email: [email protected]

Glenn Ning Ge
Email: [email protected]


1. New Double Sided Molded Package Platform Development With Open Cavity Mold on One Side and Exposed Die Mold on the Other Side
MiKyeong Choi — Amkor Technology Korea
HoSeung Seo — Amkor Technology Korea
SeMin Gim — Amkor Technology Korea
GyeongCheol Lee — Amkor Technology Korea
JungHoon Na — Amkor Technology Korea
GaHyeong Hwang — Amkor Technology Korea
Ted Adlam — Amkor Technology, Inc.
Jeff Davis — Amkor Technology, Inc.
WonBae Bang — Amkor Technology Korea
KiDong Sim — Amkor Technology Korea
WonChul Do — Amkor Technology Korea
KyungRok Park — Amkor Technology Korea

2. Package Miniaturization and Wiring Impedance Reduction for High-Bandwidth Memory Devices With Vertical Wire Bonding
Keita Mochizuki — KIOXIA Corporation
Hiroyuki Wakioka — KIOXIA Corporation
Tsutomu Fujita — KIOXIA Corporation
Masatoshi Shomura — KIOXIA Corporation
Takeori Maeda — KIOXIA Corporation
Toshihiko Ohda — KIOXIA Corporation
Yoshitaka Muto — KIOXIA Corporation
Eiji Takano — KIOXIA Corporation
Masahiro Inohara — KIOXIA Corporation

3. Ultra-Thin Double Side SiP Technology With Embedded Trace Substrate
Chehan (Jerry) Li — Renesas Electronics Corporation
Jesus Mennen Belonio — Renesas Electronics Corporation
Jon Gutierrez — Renesas Electronics Corporation
Humi (Shih-Wen) Tang — Renesas Electronics Corporation
Jessie (Yu-Shan) Wei — Renesas Electronics Corporation

4. High Accuracy Selective Patterning for EMI Shielding of 5G AiP
Ming-Hung Chen — Advanced Semiconductor Engineering, Inc. (US)
Huei-Pin Chien — Advanced Semiconductor Engineering, Inc. (US)
Yi-Chun Chou — Advanced Semiconductor Engineering, Inc. (US)
Yu-Shuan Tsai — Advanced Semiconductor Engineering, Inc. (US)
Kuan-Lin Kuo — Advanced Semiconductor Engineering, Inc. (US)
Jei-Chieh Kao — Advanced Semiconductor Engineering, Inc. (US)

5. Analysis of Thin Flip Chip Chip-Scale Package Warpage Causes and Variations
Chee S Foong — NXP Semiconductor, Inc.
Amirul Afripin — NXP Malaysia Sdn. Bhd.
Nishant Lakhera — NXP Semiconductor, Inc.
Trent Uehling — NXP Semiconductor, Inc.

6. Large Package Body Size Scaling With Two Novel Technologies: Multi Ball BGA and Liquid Metal Interconnect
Xiao Lu — Intel Corporation
Jiaqi Wu — Intel Corporation
Sangeon Lee — Intel Corporation
Karumbu Meyyappan — Intel Corporation

7. A Study About Direct Laser Reflow for Forming Stable and Reliable C4 Bump Interfaces on Semiconductor Substrates for Flip Chip Applications
Matthias Fettke — Pac Tech GmbH
Anne Fisch — Pac Tech GmbH
Alexander Frick — Pac Tech GmbH
Georg Friedrich — Pac Tech GmbH
Thorsten Teutsch — Pac Tech GmbH