Technical Program

Program Sessions: Wednesday May 29th 9:30 AM – 12:35 PM

Session 1: Advances in Fan-Out, Wafer-Level, and Panel-Level Packaging Technologies Enabling New Applications
Committee: Packaging Technologies
Room: Aurora B

Session Co-Chairs:

Beth Keser
ZeroASIC
Email: [email protected]

Steffen Kroehnert
ESPAT Consulting
Email: [email protected]

Papers:

1. How to Manipulate Warpage in Fan-Out Wafer and Panel Level Packaging
Tanja Braun — Fraunhofer IZM
Ole Hölck — Fraunhofer IZM
Marius Adler — Fraunhofer IZM
Mattis Obst — Fraunhofer IZM
Steve Voges — Fraunhofer IZM
Karl-Friedrich Becker — Fraunhofer IZM
Rolf Aschenbrenner — Fraunhofer IZM
Marcus Voitel — Technical University Berlin
Marc Dreissigacker — Technical University Berlin
Martin Schneider-Ramelow — Technical University Berlin

2. Advanced FO-PLP with Multi-chip for Wearable Application
Jooyoung Choi — Samsung Electronics Co., Ltd.
Hyungmin Kim — Samsung Electronics Co., Ltd.
Jaehoon Choi — Samsung Electronics Co., Ltd.
Eun Seok Choi — Samsung Electronics Co., Ltd.
Hwanpil Park — Samsung Electronics Co., Ltd.
Gyunghwan Oh — Samsung Electronics Co., Ltd.
Seungsoo Ha — Samsung Electronics Co., Ltd.
Wonkyung Choi — Samsung Electronics Co., Ltd.
Dong Wook Kim — Samsung Electronics Co., Ltd.

3. Transcending the Reticle Limit in On-Wafer Die Integration and Advanced Packaging: Full-Wafer Patterning With High-Productivity Electron Beam Lithography
Andrew Ceballos — Multibeam Corporation
Kenneth MacWilliams — Multibeam Corporation
Ted Prescop — Multibeam Corporation
Tsenguun Byambadorj — Multibeam Corporation
David Lam — Multibeam Corporation
Timothy Michalka — TLM Technologies, LLC
Craig Bishop — Deca Technologies, Inc.
Cliff Sandstrom — Deca Technologies, Inc.
Tim Olson — Deca Technologies, Inc.

4. 600 mm x 600 mm Fan-Out Panel Level Package (FOPLP) as an Alternative to Lead-Frame-Free Quad Flat No Lead (QFN) Package
Jacinta Aman Lim — nepes Corporation
Yoon Muk Park — nepes Corporation
Brett Dunlap — nepes Corporation
Jane Lee — nepes Corporation
Robin Davis — DECA

5. Challenges and Analysis for Pitch 25 µm - 100 µm Mixed Micro Bumps and Interconnection in Fan-Out Embedded Bridge Die With TSV Package (FO-EB-TSV)
Kuei Hsiao Kuo — Siliconware Precision Industries Co., Ltd.
Jia Han Li — Siliconware Precision Industries Co., Ltd.
Chia Shing Wu — Siliconware Precision Industries Co., Ltd.
Feng Lung Chien — Siliconware Precision Industries Co., Ltd.

6. High Precision and Productivity Bridge-Die-Last Bonding Process and Its Reliability for Pillar-Suspended Bridge (PSB) Architecture
Ichiro Kono — AOI Electronics
Yoshihiro Kometani — AOI Electronics
Atsushi Kuroha — AOI Electronics
Yoichiro Kurita — Tokyo Institute of Technology

7. Vertical Fan-Out (VFO) Package With Enhanced Form Factor and Performances for Mobile Applications
Kijun Sung — SK Hynix, Inc.
Kyoungtae Eun — SK Hynix, Inc.
Seowon Lee — SK Hynix, Inc.
Sungwon Yoon — SK Hynix, Inc.
Ho-Young Son — SK Hynix, Inc.
Kang-Wook Lee — SK Hynix, Inc.